1. Field of the Invention
This invention relates generally to the field of data processing systems and more specifically relates to arrangements for interconnecting the various units forming such a system to enable the rapid and accurate transfer of information among the units. More particularly, the invention relates to an arrangement for transferring information relating to faults or errors in a digital data processing system to facilitate speedy recovery from such faults.
2. Description of the Prior Art
A digital data processing system generally includes three basic elements: a memory element, an input/output element, and a processor element, all of which are interconnected by one or more buses. The memory element stores information, which comprises both data and instructions for processing the data, in addressable storage locations. The processor element retrieves data and instructions from the memory element, processes the data in accordance with the instructions, and returns the processed data to the memory element. Input/output elements include such units as operator consoles, printers, and teletypewriters, by which information may be loaded into and obtained from the system by an operator, and secondary memory storage units such as disk or tape drives which store large amounts of information that can be shifted into and out of the memory element for processing. The processor element can communicate with the input/output elements to initiate these information transfer operations, and the input/output elements can also communicate with the memory element to perform the information transfer.
When certain events occur in the units comprising the data processing system, the unit can "interrupt" the processor element to permit it to ascertain the nature of the event and to perform certain operations which may be necessitated by the event. For example, a disk drive may initiate an interrupt when it has finished performing control operations such as seeks or searches, in which the recording head is moved to the track of the disk which contains the desired information and the disk is rotated until a desired portion of the track has moved under the head. This allows the processor to then initiate a transfer of that information into memory. The disk drive may also interrupt the processor when the transfer is completed, to inform it that the information is now available in memory for processing and that the disk drive itself is also available for other operations. In addition, units may request interrupts in the event of errors or malfunctions that are detected in the operation of the unit requesting the interrupt and in the transfer of information between units over the bus.
When an interrupt request is received, the processor element, when it recognizes, or grants, the interrupt, goes through a lengthy preparatory process of first saving its prior processing state by transmitting the contents of certain of its processing registers to memory, and of retrieving a control program from memory for processing the interrupt. While it is processing the control programs, the processor cannot process user programs, which can reduce the throughput of the system. In some cases the processor may, in fact, be waiting for an interrupt; for example, if the prbcessor is waiting for data stored on a disk drive to be transferred into memory so that it can process the data, the interrupt may indicate to the processor that it can continue processing user programs or begin processing other user programs. However, if the interrupts are the result of errors, such as, for example, information transfer errors, requiring the processor to devote attention to the error may waste the processor's time as the problem may be intermittent and be corrected by the units repeating the transfer operation.
To enable units to repeat transfer operations, in recent years, buses connecting the units in a data processing system have been designed to transmit an acknowledgement or confirmation signal whereby a receiving unit indicates whether the information transfer was properly received. The confirmation signal is typically sent a selected time after the transfer of the information, as described in U.S. Pat. No. 4,232,366 entitled "Bus For Data Processing System With Overlap Sequences", issued to John V. Levy, et al, on Nov. 4, 1980, and assigned to the assignee of the present invention. That patent discloses a bus that is synchronous in operation, that is, it has a single globally-generated clock signal that controls all transfers over the bus. In that bus, a confirmation signal is sent two clock cycles after the corresponding information transfer. During the delay, certain features of the information transferred can be verified such as decoding of an address and checking of parity.
Similarly, U.S. Pat. No. 3,997,896, issued to Frank V. Cassarino, Jr., et al, on Dec. 14, 1976, entitled "Data Processing System Providing Split Bus Operation", discloses a data processing system interconnected by an asynchronous bus, that is, one which does not provide a globally-generated clocking signal that controls transfers over the bus. The bus disclosed in that patent uses a handshake signal to time information transfers between units connected to the bus. In that patent, a portion of the asynchronous handshake constitutes a the confirmation signal for the information transfer.
However, in either system, if the receiving unit determines that a problem has arisen and that it is unable to perform an operation required by the transfer after it has sent the confirmation signal, the unit may also be unable to indicate to either the transmitting unit or to the processor that a problem has occurred. For example, memory controllers are generally not designed to request interrupts, instead relying on the transmission of the confirmation signal to indicate whether an error has occurred. However, in pipelined controllers, which can buffer a number of memory requests and the accompanying data after they have been received and before they can be processed, an example of which is also described in the above-mentioned Levy, et al, patent, the confirmation signals normally must be transferred before the memory request is completed. However, errors can occur while the memory requests are in the buffer. Typically, there is no way for the memory controller to indicate that such errors have occurred. While it would be possible to allow these memory controllers to interrupt the processor in the event of such an error, in many circumstances this would merely be a waste of processor time, as usually all that need be done is to have the transmitting unit retransmit the request and data.